There is a general limit to the linearity of an output signal from a power amplifier used for wireless transmission. Particularly, when the level of the input signal is large, a reduction in gain occurs (i.e., non-linear distortion). Cartesian feedback linearization apparatuses have been established as one type of circuit that compensates for such non-linear distortion. If a Cartesian feedback linearization apparatus is functioning ideally, then a high degree of linearity is achieved in the output signal from the power amplifier.
In a Cartesian feedback linearization apparatus, the output signal from the power amplifier is taken and fed back into the input side. At this point, feedback-related phase changes are produced due to factors such as, for example, effects on antenna load and propagation delays in directional couplers and demodulators. Accordingly, it is desirable to correct such feedback-related phase changes in order to enable effective operation of the Cartesian feedback linearization apparatus.
From this perspective, there exists a phase correction apparatus applied to a Cartesian feedback linearization apparatus. FIG. 1 illustrates the core configuration of such a phase correction apparatus.
In FIG. 1, the in-phase component I and the quadrature component Q of a transmission baseband signal are modulated by a quadrature modulator 40 before being combined. The combined signal is then amplified to a desired level by a power amplifier (PA) 90, and transmitted as an RF signal (RF_OUT). In addition, part of the RF signal (RF_OUT) is taken (i.e., fed back) by a directional coupler, and from this feedback signal y(t) a baseband signal (in-phase component I*, quadrature component Q*) is generated by a quadrature demodulator 30. Due to the feedback-related phase changes described above, I≠I*, and Q≠Q* (in FIG. 1, the delay equivalent to the phase changes is expressed as the delay time τ). For this reason, a phase correction apparatus for correcting the phase changes is provided.
In FIG. 1, the phase correction apparatus is provided with a phase detector and a phase shifter 104. The phase detector includes a sine detector 101 and a cosine detector 102. If the target correction amount for the phase (i.e., the phase error) is taken to be Δφ, then the fed-back baseband signal (in-phase component I*, quadrature component Q*) is expressed by the following Eqs. 1 and 2. In Eqs. 1 and 2, the relationships I=I* and Q=Q* hold true only when Δφ=0. In addition, sin(Δφ) is computed in the sine detector 101 according to the following Eq. 3. Herein, k in Eq. 3 is a normalization constant, where k=1/(I·I+Q·Q).I*=I·cos(Δφ)+Q·sin(−Δφ)  (1)Q*=I·sin(Δφ)+Q·cos(Δφ)  (2)sin(Δφ)=k·(I·Q*−Q·I*)  (3)
The cosine detector 102 computes cos(Δφ) according to the relationship cos(Δφ)=(1−sin2(Δφ))1/2. The cosine detector 102 is also configured such that the sum of the squares of the input into the phase shifter 104 becomes a predetermined constant Mag. In so doing, the amplitude of the output signal from the phase shifter 104 is compensated so as to become fixed.
As illustrated by the following Eq. 4, the phase shifter 104 takes both a carrier wave signal sin(ωt) from a local oscillator, as well as a signal obtained by phase-shifting the carrier wave signal by π/2. The phase shifter 104 multiplies the above signals by cos(Δφ) and sin(Δφ), respectively, and then combines the result. As a result, the quadrature modulator 40 is supplied with the signal sin(ωt+Δφ), which is equivalent to the carrier wave signal sin(ωt) from the local oscillator being phase-shifted forward by Δφ. Consequently, the phase error becomes 0 (i.e., Δφ=0) between the RF signal y(t) that was fed back from the output of the wireless transmitter, and the carrier wave signal supplied by the quadrature modulator 40.cos(Δφ)·sin(ω·t)+sin(Δφ)·cos(ω·t)=sin(ω·t+Δφ)  (4)
However, the phase correction apparatus described with reference to FIG. 1 is configured such that the phase detector and the phase shifter are realized by analog circuits. For this reason, operation might become unstable, due to factors such as temperature drift in the characteristics of elements within the analog circuits, and offset characteristics produced at the time of manufacturing.